1. Field of the Invention
The present invention relates to a PLL (Phase Locked Loop) frequency synthesizer which outputs a plurality of signals having a plurality of frequencies.
2. Description of the Related Art
In order to concurrently output a plurality of signals having a plurality of frequencies in the conventional PLL frequency synthesizers, it is necessary to provide a plurality of PLL circuits.
FIG. 8 is a block diagram illustrating a conventional PLL frequency synthesizer. The PLL frequency synthesizer of FIG. 8 comprises reference-signal generators 101a and 101b, reference counters 102a and 102b, phase comparators 103a and 103b, charge pumps 104a and 104b, low-pass filters (LPFs) 105a and 105b, voltage-controlled oscillators 106a and 106b, and programmable counters 107a and 107b. 
The reference-signal generator 101a, the reference counter 102a, the phase comparator 103a, the charge pump 104a, the LPF 105a, the voltage-controlled oscillator 106a, and the programmable counter 107a constitute a first PLL circuit, and the reference-signal generator 101b, the reference counter 102b, the phase comparator 103b, the charge pump 104b, the LPF 105b, the voltage-controlled oscillator 106b, and the programmable counter 107b constitute a second PLL circuit. Thus, two signals having two different frequencies f1 and f2 are outputted from the first and second PLL circuits, respectively.
The reference-signal generators 101a and 101b output reference signals. The reference counters 102a and 102b divide the frequencies of the reference signals outputted from the reference-signal generators 101a and 101b, and output frequency-divided reference signals having the frequencies fr1 and fr2, respectively. The phase comparator 103a detects and outputs the phase difference between a signal outputted from the programmable counter 107a and the frequency-divided reference signal outputted from the reference counter 102a, and the phase comparator 103b detects and outputs the phase difference between the signal outputted from the programmable counter 107b and the frequency-divided reference signal outputted from the reference counter 102b. Currents proportional to the phase differences outputted from the phase comparators 103a and 103b flow into or out of the charge pumps 104a and 104b. The low-pass filters (LPFs) 105a and 105b smooth the currents outputted from the charge pumps 104a and 104b, and generate DC (direct-current) voltages as control voltages, respectively. The voltage-controlled oscillators 106a and 106b output signals having the frequencies f1 and f2 according to the control voltages outputted from the low-pass filters (LPFs) 105a and 105b, respectively. The programmable counters 107a and 107b divide the frequencies f1 and f2 of the signals outputted from the voltage-controlled oscillators 106a and 106b, and output frequency-divided signals to the phase comparators 103a and 103b, respectively.
Since the reference signals outputted from the reference-signal generators 101a and 101b are different, the frequencies f1 and f2 of the signals outputted from the voltage-controlled oscillators 106a and 106b are different. Thus, signals having a plurality of frequencies are concurrently obtained by providing a plurality of PLL circuits.
However, the necessity for provision of the plurality of PLL circuits in the conventional PLL frequency synthesizer illustrated in FIG. 8 increases the number of circuit components and the circuit area. In order to overcome this problem, for example, Japanese Unexamined Patent Publication No. 63-209223 (pages 2 and 3 and FIG. 1) discloses a PLL frequency synthesizer in which some portions of PLL circuits are shared so that the number of circuit components is reduced and increase in the circuit area is suppressed.
FIG. 9 is a block diagram illustrating another conventional PLL frequency synthesizer. The PLL frequency synthesizer of FIG. 9 comprises a phase comparator 111, switches 112 and 115, low-pass filters (LPFs) 113a and 113b, voltage-controlled oscillators 114a and 114b, a programmable counter 116, and a controller 117.
The phase comparator 111 receives a reference signal having the frequency fr, and outputs the phase difference between the reference signal and the signal outputted from the programmable counter 116. The switch 112 is controlled by the controller 117, and outputs to the low-pass filters (LPFs) 113a and 113b the phase difference outputted from the phase comparator 111. Each of the low-pass filters (LPFs) 113a and 113b smoothes the phase difference outputted from the switch 112 to the LPF, and generates a control voltage. The voltage-controlled oscillators 114a and 114b output signals having the frequencies f1 and f2 according to control signals outputted from the low-pass filters (LPFs) 113a and 113b, respectively. The switch 115 is controlled by the controller 117, and outputs to the programmable counter 116 one of the signals outputted from the voltage-controlled oscillators 114a and 114b. The programmable counter 116 is controlled by the controller 117, and divides the frequency of the signal outputted from the switch 115.
The controller 117 controls the switches 112 and 115 and the programmable counter 116 so that the signals having the frequencies f1 and f2 are concurrently outputted from the voltage controlled oscillators 114a and 114b. In order to output the signal having the frequency f1, the controller 117 controls the switch 112 so as to connect the phase comparator 111 and the LPF 113a, and the switch 115 so as to connect the programmable counter 116 and the voltage-controlled oscillator 114a. In addition, in order to output the signal having the frequency f2, the controller 117 controls the switch 112 so as to connect the phase comparator 111 and the LPF 113b, and the switch 115 so as to connect the programmable counter 116 and the voltage-controlled oscillator 114b. Further, the controller 117 controls the frequency-division ratio of the programmable counter 116 so that the signals having the frequencies f1 and f2 are outputted. As described above, the phase comparator 111 and the programmable counter 116 are shared, and the controller 117 is provided, so that the number of circuit components is reduced and increase in the circuit area is suppressed.
Further, for example, Japanese Unexamined Patent Publication No. 7-95069 (paragraph Nos. 0018 to 0022 and FIG. 1) discloses a PLL frequency synthesizer in which the frequency is locked at a plurality of values which are set as data at a plurality of channels, and the control voltages of a voltage-controlled oscillator when the frequency is locked at the plurality of values are stored in advance. When a signal having the frequency corresponding to one of the above channels is outputted, the corresponding control voltage is outputted to the voltage-controlled oscillator, so that the lockup time can be reduced.
Nevertheless, in the PLL frequency synthesizer disclosed in Japanese Unexamined Patent Publication No. 63-209223, it is necessary to increase the time constants of the LPFs in order to stabilize the output signals after power-on, so that the lockup time increases.
In addition, since the PLL frequency synthesizer disclosed in Japanese Unexamined Patent Publication No. 7-95069 contains a storage circuit for storing the control voltages and a converter for performing analog-to-digital conversion and digital-to-analog conversion of the control voltages, the number of circuit components and the circuit area increase.